Page 21 - Krész, Miklós, and Andrej Brodnik (eds.). MATCOS-13. Proceedings of the 2013 Mini-Conference on Applied Theoretical Computer Science. Koper: University of Primorska Press, 2016.
P. 21
ew method for transforming algorithm into VHDL by
starting from a Haskell functional language description
Gergely Suba ∗
Budapest University of Technology and Prof. Dr. Péter Arató
Economics
Budapest University of Technology and
2 Magyar tudósok körútja Economics
Budapest, Hungary, 1117
2 Magyar tudósok körútja
sugergo@iit.bme.hu Budapest, Hungary, 1117
ABSTRACT arato@iit.bme.hu
In the field of computer engineering, there are a lot of prob- 1. INTRODUCTION
lems that are too time-consuming like biological or physical
calculations and that’s why they have to be implemented Although the speed of the conventional processors is growing
using special hardware structures. Usually, these hardware continually, there are a lot of problems that are too time-
structures are described in HDL (Hardware Description Lan- consuming like biological or physical computing and that’s
guage). Developing in HDL languages is not as efficient as why they have to be implemented in a more efficient hard-
it would be in case of software languages due to its low level ware structure and sometimes in special hardware. Usually,
structures. these hardware structures are described in HDL (Hardware
Description Language). These languages are not so well-
The aim of this work is to implement and test a method known by the mathematicians and software engineers, they
(a compiler program), where the starting point is a code usually write the algorithms in general-purpose program-
written in the functional language Haskell and the output ming languages. There is a great difference between using
is the same algorithm in VHDL (a kind of HDL) language. HDL or software languages, and the chance to transform
The main advantage of the novel method presented in this these two representations into each other is rather small. To
paper is that it generates a synthesizable VHDL description overcome this gap, there is plenty of research that are very
from Haskell code automatically for FPGA implementation. important parts of the so called System Level Synthesis.
The method introduced in this paper can solve two sepa- Hardware synthesis starting with a functional software lan-
rate problems: 1) running algorithms effectively in FPGA, guage has some advantages compared to a hardware descrip-
2) development of digital hardware implementing a speci- tion language. Besides, modifying the hardware when the
fied function. We demonstrate the efficiency of the method algorithm changes is easier, because a code written in func-
through practical examples like a part of the MP3 decoding tional language can be adapted more directly than one writ-
algorithm. ten in a hardware description language. Transforming an
algorithm to HDL can be easily automated by the novel com-
Categories and Subject Descriptors piler program introduced in this paper. The program code
written in functional language can be run in PC, therefore
C.3 [Special Purpose and Application-based Systems]: it can be tested easily. In contrast to this, the hardware de-
Real-time and embedded systems; D.2.2 [Software Engi- scription languages require a complex simulation for testing,
neering]: Design Tools and Techniques where the inputs and outputs are handled as digital signals,
which is an additional complication.
Keywords
Based on the above arguments, the aim of this work is to
HLS, FPGA, Haskell, VHDL, dataflow graph implement and test a method (a compiler program), where
the starting point is a code written in a functional language
∗Prof. Dr. P´eter Arato´ is the supervisor. and the output is the same algorithm in HDL language.
Department of Control Engineering and Information Tech- Functional languages have benefits in case of digital signal
nology, Faculty of Electrical Engineering and Informatics processing and it fits the capabilities of the hardware world
better than the imperative ones. I focus on the Haskell [9]
functional language, which is being developed dynamically,
and it supports the research work well.
The main advantage of the method presented in this paper
is that it generates the synthesizable VHDL [6] description
from Haskell code automatically for FPGA implementation.
Even a pipeline optimization tool can be involved by the pro-
cedure such as the high level synthesis tool PIPE, developed
at the Department of Control Engineering and Information
Technology in BME.
m a t c o s -1 3 Proceedings of the 2013 Mini-Conference on Applied Theoretical Computer Science 21
Koper, Slovenia, 10-11 October
starting from a Haskell functional language description
Gergely Suba ∗
Budapest University of Technology and Prof. Dr. Péter Arató
Economics
Budapest University of Technology and
2 Magyar tudósok körútja Economics
Budapest, Hungary, 1117
2 Magyar tudósok körútja
sugergo@iit.bme.hu Budapest, Hungary, 1117
ABSTRACT arato@iit.bme.hu
In the field of computer engineering, there are a lot of prob- 1. INTRODUCTION
lems that are too time-consuming like biological or physical
calculations and that’s why they have to be implemented Although the speed of the conventional processors is growing
using special hardware structures. Usually, these hardware continually, there are a lot of problems that are too time-
structures are described in HDL (Hardware Description Lan- consuming like biological or physical computing and that’s
guage). Developing in HDL languages is not as efficient as why they have to be implemented in a more efficient hard-
it would be in case of software languages due to its low level ware structure and sometimes in special hardware. Usually,
structures. these hardware structures are described in HDL (Hardware
Description Language). These languages are not so well-
The aim of this work is to implement and test a method known by the mathematicians and software engineers, they
(a compiler program), where the starting point is a code usually write the algorithms in general-purpose program-
written in the functional language Haskell and the output ming languages. There is a great difference between using
is the same algorithm in VHDL (a kind of HDL) language. HDL or software languages, and the chance to transform
The main advantage of the novel method presented in this these two representations into each other is rather small. To
paper is that it generates a synthesizable VHDL description overcome this gap, there is plenty of research that are very
from Haskell code automatically for FPGA implementation. important parts of the so called System Level Synthesis.
The method introduced in this paper can solve two sepa- Hardware synthesis starting with a functional software lan-
rate problems: 1) running algorithms effectively in FPGA, guage has some advantages compared to a hardware descrip-
2) development of digital hardware implementing a speci- tion language. Besides, modifying the hardware when the
fied function. We demonstrate the efficiency of the method algorithm changes is easier, because a code written in func-
through practical examples like a part of the MP3 decoding tional language can be adapted more directly than one writ-
algorithm. ten in a hardware description language. Transforming an
algorithm to HDL can be easily automated by the novel com-
Categories and Subject Descriptors piler program introduced in this paper. The program code
written in functional language can be run in PC, therefore
C.3 [Special Purpose and Application-based Systems]: it can be tested easily. In contrast to this, the hardware de-
Real-time and embedded systems; D.2.2 [Software Engi- scription languages require a complex simulation for testing,
neering]: Design Tools and Techniques where the inputs and outputs are handled as digital signals,
which is an additional complication.
Keywords
Based on the above arguments, the aim of this work is to
HLS, FPGA, Haskell, VHDL, dataflow graph implement and test a method (a compiler program), where
the starting point is a code written in a functional language
∗Prof. Dr. P´eter Arato´ is the supervisor. and the output is the same algorithm in HDL language.
Department of Control Engineering and Information Tech- Functional languages have benefits in case of digital signal
nology, Faculty of Electrical Engineering and Informatics processing and it fits the capabilities of the hardware world
better than the imperative ones. I focus on the Haskell [9]
functional language, which is being developed dynamically,
and it supports the research work well.
The main advantage of the method presented in this paper
is that it generates the synthesizable VHDL [6] description
from Haskell code automatically for FPGA implementation.
Even a pipeline optimization tool can be involved by the pro-
cedure such as the high level synthesis tool PIPE, developed
at the Department of Control Engineering and Information
Technology in BME.
m a t c o s -1 3 Proceedings of the 2013 Mini-Conference on Applied Theoretical Computer Science 21
Koper, Slovenia, 10-11 October
